Estimation of Short Circuit Power Dissipation in CMOS Inverter

Abstract

Optimization of high speed CMOS circuit is to discover the variation in physical parameters, which affects the circuit performance. T-sizing is one such method to analyze the parameter variation. A considerable part of energy dissipation in CMOS is due to short circuit currents. The channel length of the transistors is fixed and the size of the transistor is defined by its width. Decreasing the channel length and gate oxide thickness increases transconductance, i.e., the current drive of the transistor. The proposed work is a compact model for the short circuit power dissipation, which deals with the analytical formulation of short circuit power dissipation and also to reduce the power consumption of CMOS inverter. In order to minimize the signal delay the transistor parameters has to be varied accordingly. Dynamic power is taken into considerations because static power is negligible. The energy model presented in this work accounts the influences of input voltage transition time, transistor sizes ,device carrier velocity saturation ,narrow ? width effects ,gate drain ,short circuiting transistor?s gate source capacitances and output load dissipation using MATLAB software which calculates the voltage and current as a function of time when a large signal is applied.